Department of Electrical and Electronics Engineering

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Subject: search.filters.subject.Architecture

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Now showing 1 - 8 of 8
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    Security in IoT-enabled smart agriculture: architecture, security solutions and challenges
    (Springer, 2022-04) Chamola, Vinay
    Agricultural industry is one of the most vital industries that has a major contribution to the economy due to its share in the Gross Domestic Product (GDP) and as a source of employment. The past few decades have seen immense change in the operation of agricultural sector with the introduction of precision farming in conjunction with Internet of Things (IoT). The application of such advancements is highly based on exchange of messages between various devices in the farming. This paper aims to study the security scenarios applicable in husbandry through the analysis of possible attacks and threats. The testbeds available for agriculture based on IoT have been studied. An architecture for smart farming is proposed which is independent of the underlying technologies that may be used and the requirements of security have been laid out based on the proposed architecture. A literature survey of security protocols for various subsectors of security in smart agriculture along with authentication protocols in smart applications provides a detailed direction of the progress in each of farming security sub-areas and identifies the dearth of existing protocols. The current progress in development of IoT-based tools and systems from industry has also been studied.
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    Nonlinear Motion Tracking by Deep Learning Architecture
    (IOP, 2018) Gupta, Karunesh Kumar
    In the world of Artificial Intelligence, object motion tracking is one of the major problems. The extensive research is being carried out to track people in crowd. This paper presents a unique technique for nonlinear motion tracking in the absence of prior knowledge of nature of nonlinear path that the object being tracked may follow. We achieve this by first obtaining the centroid of the object and then using the centroid as the current example for a recurrent neural network trained using real-time recurrent learning. We have tweaked the standard algorithm slightly and have accumulated the gradient for few previous iterations instead of using just the current iteration as is the norm. We show that for a single object, such a recurrent neural network is highly capable of approximating the nonlinearity of its path
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    State of the Art and Trends in Electric and Hybrid Electric Vehicles
    (IEEE, 2021-05) Bansal, Hari Om
    Electric and hybrid electric vehicles (EV/HEV) are promising solutions for fossil fuel conservation and pollution reduction for a safe environment and sustainable transportation. The design of these energy-efficient powertrains requires optimization of components, systems, and controls. Controls entail battery management, fuel consumption, driver performance demand emissions, and management strategy. The hardware optimization entails powertrain architecture, transmission type, power electronic converters, and energy storage systems. In this overview, all these factors are addressed and reviewed. Major challenges and future technologies for EV/HEV are also discussed. Published suggestions and recommendations are surveyed and evaluated in this review. The outcomes of detailed studies are presented in tabular form to compare the strengths and weaknesses of various methods. Furthermore, issues in the current research are discussed, and suggestions toward further advancement of the technology are offered. This article analyzes current research and suggests challenges and scope of future research in EV/HEV and can serve as a reference for those working in this field.
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    Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders
    (Emerald, 2005-12) Gupta, Anu; Shekhar, Chandra
    The objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraints
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    Dual channel addition based FFT processor architecture for signal and image processing
    (ACM Digital Library, 2009-12) Gupta, Anu; Shekhar, Chandra; Asati, Abhijit
    This paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fourier transform. Since multipliers are very power hungry elements in VLSI designs, they result in significant power consumption. So, the complex multiplication operations are realised using shift-and-add operations. The proposed algorithm performs all intermediate addition operation using a novel dual channel addition technique, which avoids carry propagation delay. Only in the last stage, carry look ahead adders are used to give final result. This dual channel addition algorithm reduces the critical delay path by 42% and 38.29% as compared to traditional and Maharatna approach respectively.
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    Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation
    (IET, 2018-10) Gupta, Anu; Asati, Abhijit
    This study presents a circle Hough transform (CHT) architecture that provides memory reduction between 74 and 93% without and with little degradation in the accuracy, respectively. For an image of P × Q pixels, the standard (direct) CHT requires a two-dimensional (2D) accumulator array of P × Q cells, but the proposed CHT uses a 2D accumulator array of (P/m) × (Q/n) cells for coarse circle detection and two 1D accumulator arrays of P × 1 and Q × 1 cells for fine detection, therein reducing the memory by a factor of m × n (approximately). The proposed CHT architecture was applied to iris localisation application and carried out its comprehensive evaluation. The average accuracy of the proposed CHT for iris localisation (inner plus outer iris-circle detection) is 98% with memory reduction of 87% compared with the direct CHT. The proposed CHT architecture was implemented on field programmable logic array targeting Xilinx Zynq device. The proposed CHT hardware takes processing time of 6.25 ms (average) for iris localisation in an image of 320 × 240 px2. The proposed work is compared with the previous work, which shows improved results. Finally, the effect of additive Gaussian noise on the CHT performance is investigated.
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    Estimation of Optimal Buffering parameters for dynamic traffic intensity and its Architectures
    (2005) Chaubey, V.K.
    In this paper, we have undertaken the mathematical formulation for determining the required buffering time based on the traffic intensity on an all-optical network. The effect of design parameters on optical network containing proper buffer and control circuitry has been evaluated. Some of the buffering architectures have been suggested to provide different buffering times as governed by the diurnal traffic requirements
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    A New XOR-Free Approach for Implementation of Convolutional Encoder
    (IEEE, 2016-03) Chaubey, V.K.
    This letter presents a new algorithm to construct an XOR-Free architecture of a power efficient Convolutional Encoder. Optimization of XOR operators is the main concern while implementing polynomials over GF(2), which consumes a significant amount of dynamic power. The proposed approach completely removes the XOR-processing operation of a chosen nonsystematic, feed-forward generator polynomial and reduces the logical operators, thereby the encoding cost. Hardware (HW) implementation of the proposed design uses Read-only memory (ROM) with a preprocessed addressing operations to reduce ROM size by nearly 50%. The results of the new architecture reduce the dynamic power up to 21.4% and HW cost up to 15% with lesser design complexity as compared to conventional method. The Hardware cosimulation of the architecture is first validated and then implemented with Xilinx Virtex-V FPGA.