Department of Electrical and Electronics Engineering

Permanent URI for this collectionhttp://localhost:4000/handle/123456789/1925

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Subject: search.filters.subject.High-level synthesis (HLS)

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Now showing 1 - 5 of 5
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    Area-optimal FPGA implementation of the YOLO v2 algorithm using High-Level Synthesis
    (IEEE, 2020) Asati, Abhijit; Shekhar, Chandra
    Field-programmable gate arrays (FPGAs) have been used as pre-silicon validation platforms in VLSI designs. In this paper, we propose a FPGA-based you-only-look-once (YOLO) v2 object detector implementation that provides better performance in terms of speed, achieves higher accuracy, and requires fewer resources compared with the alternatives. It is constructed using a convolutional deep neural network (CNN). We apply high-level synthesis (HLS) to model and optimize the implementation using multiple directives, such as pipelining, loop unrolling, in-lining, etc. The proposed YOLO v2 design is implemented on a Xilinx Zynq xc7z020clg484-1 device. We run simulations to test its functionality using an xSim simulator. The proposed implementation not only runs faster, but it utilizes an order of magnitude fewer resources than available implementations in the literature.
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    High-Level synthesis assisted design and verification framework for automotive radar processors
    (Elsevier, 2020-10) Asati, Abhijit; Shekhar, Chandra
    In radar-based advanced driver assistance systems, baseband processing is necessary to detect the speed, distance, and angle of elevation of the target (e.g., vehicle, pedestrian, traffic sign, etc.). The target and the source often move at high speeds; therefore, the computation rate must be sufficiently high to perform actions (e.g., braking) in real-time. Software-based implementations of such systems fall short of the required performance, which has led to an increase in the popularity of custom hardware implementations, e.g., on field-programmable gate arrays (FPGAs). FPGAs also serve as platforms to develop software concurrent with system-on-chip (SoC) development, thereby decreasing the time to market. High-level synthesis (HLS) tools are gaining considerable attention in the very-large-scale integration design community because of their flexibility. In this paper, we propose a novel design and verification framework for a RADAR processing SoC. The framework is assisted by an HLS-based design scheme for the processor and supports the application of a real-world stimulus to register transfer-level design implementation running on FPGAs. Customer use cases for the distance and velocity calculations are executed in a pre-silicon environment using range and Doppler processing on the Xilinx Kintex-7(XC 7K 480T) FPGA. Our findings show that the proposed framework, based on MATLAB HDL Coder and HDL Verifier, is superior to similar implementations from prior research in terms of speed and FPGA resources. This is owing to the usage of appropriate HLS directives and the usage of a novel design method based on application-specific bit width for intermediate data nodes.
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    Hardware software co-design using profiling and clustering
    (IEEE, 2012) Asati, Abhijit
    The digital system design process can be accelerated by concurrent design of hardware and software. This process requires the migration of functions that are computational extensive to hardware. This paper presents a framework for identifying such functions by proposing an algorithm. The framework uses the time profiling and clustering technique to achieve the objectives. Open source spark compiler has been used to convert functions to hardware description language The final interfacing has been done in embedded development kit
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    Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications
    (Springer, 2020-11) Asati, Abhijit; Shekhar, Chandra
    In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.
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    RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications
    (Springer, 2020-07) Asati, Abhijit; Shekhar, Chandra
    Connected smart vehicles in automotive industries have increased, resulting in high vehicle-to-vehicle, vehicle-to-infrastructure, and vehicle-to-cloud connectivity. Increased data rates are required to achieve high bandwidth requirements to support such communication networks. Despite having numerous advantages, high connectivity between devices poses threats to vehicle and human security, rendering encryption critical before transmitting data across vehicular networks. Advanced encryption standard (AES) is commonly used for data encryption in automotive microcontrollers. Owing to modern digital design complexities, field-programmable gate arrays (FPGAs) are attracting attention for pre-silicon verification and software development. Owing to their parallel architectures, FPGAs are ideal for prototyping automotive designs running encryption algorithms, like AES at real-time data rates. Moreover, because they are reconfigurable, prototyping results of different implementation choices can be verified at an early stage, thereby helping architects and designers with forthcoming optimal designs. FPGAs also serve as platforms to develop software considerably before silicon arrives, thereby decreasing the time to market. Herein, we propose a high-throughput FPGA implementation of the AES algorithm for automotive microcontrollers using a 128-bit key created via Vivado high-level synthesis (HLS) tool. We use HLS design method based on application-specific bit widths to implement the design on FPGA. The generated design is implemented and verified using Xilinx Kintex 7 and Virtex 6 FPGA; despite identical resource utilization (Look up tables and Flip-Flops), the throughput results are superior to those obtained previously