Department of Electrical and Electronics Engineering
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Item An Improved Power Gating Technique with Data Retention and Clock Gating(IEEE, 2021) Asati, AbhijitThe design of microelectronic power management circuits offering low power in sleep mode without degrading the performance in normal mode is stringent requirement for electronic systems design for IoT and other low power VLSI applications. The retention flip-flops are used to retain the state of a power gated combinational circuit when it enters in the SLEEP mode. In this research a improved technique to integrate power gating, data retention with additional clock gating is proposed. Further, we have analyzed power gating operation of a 4×4 array multiplier circuit with state retention in SLEEP mode along with additional clock gating operation for 32 nm and 45 nm technology nodes. The power saving analysis of a multiplier with power gating technique considering the sleep activity factor and data input frequency is also presented.Item Integrated Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes(Springer, 2021-12) Asati, AbhijitSwitching activities in a circuit results in the dynamic power dissipation of a circuit. In this work we investigated power consumption of transmission gate (TG) based D flip-flop designed using different technology nodes and power saving obtained by applying integrated clock gating (ICG) technique to this flip-flop. This work deals with implementation of a transmission gate-based D flip-flop in 3 different technology nodes, viz. 32 nm, 22 nm and 16 nm. The circuit level simulation was carried out using LTSPICE tool. The simulation result of D flip-flop shows power consumption with and without ICG at the different frequencies of operation and different data activity factors at these technology nodes. Although the power dissipation decreases with scaling down the technology node, the additional power saving may be obtained using the ICG approach at higher frequency of operation and high data activity factor, which has been investigated in this research work.Item Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes(IEEE, 2020) Asati, AbhijitDynamic power dissipation depends on the switching activity of the circuit. In this paper we analyzed power consumption of TG based D flip-flop at different technology nodes and power saving obtained by applying dynamic XOR based clock gating technique to this flip-flop. This work deals with implementation of a transmission gate based D flip-flop in 3 different technology nodes namely 32 nm, 22 nm and 16 nm. The circuit level simulation result of D flip-flop shows power consumption with and without clock gating at the several frequencies of operation and several data activity factors at these technology nodes. Although the power dissipation decreases with the lower technology node, the additional power saving may be obtained using the dynamic XOR based clock gating approach at higher frequency of operation and low data activity, which has been investigated in this research work.