Department of Electrical and Electronics Engineering
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Item A Novel Technique for Improvement of Power Supply Rejection Ratio in Amplifer Circuits(IEEE, 2009-12) Gupta, Anu; Chaturvedi, Nitin; Asati, AbhijitMost of the time, power supplies fail to provide a constant voltage supply and some external voltage signal may override on the power supply giving unwanted fluctuation at the output node. This paper discusses 3 techniques to improve the power supply rejection ratio (PSRR) in amplifier circuits. (1) Cascoding technique - cascoding increases the gain from input node to output node giving high PSRR values at low frequency. (2) Feedback technique - a negative feedback in circuits generally improves PSRR since it ensures that output follows the input signal and any other external disturbance is rejected. (3) Designing an additional circuit which could nullify the effect of the voltage gain from the power supply to the output node.Item A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers(IEEE, 2009) Gupta, AnuA very simple technique to achieve low settling time is presented. It is based on the combination of class AB differential input stages, local common-mode feedback (LCMFB), and clamping circuit which provides additional current boosting, keeping the gain-bandwidth product (GBW) nearly constant. The slew enhancement is provided by an auxiliary circuit which is activated only during transients. The design is based on the ldquoTSMC 180 nm CMOS technologyrdquoItem Design of a High Performance, Low Power, Fully Differential Telescopic Cascode Amplifier using Common-Mode Feedback Circuit(Springer, 2009-12) Gupta, AnuThis paper describes the design of a high performance, low power fully differential telescopic amplifier. As is well known, high gain differential amplifiers require an additional Common-Mode Feedback (CMFB) circuit owing to their high output impedances. This is because high output impedance makes it difficult to fix their output DC level. The additional CMFB circuitry serves the function of controlling the output common mode DC level. The telescopic amplifier designed here using CMFB circuitry is simulated using 180 nm technology in Cadence EDA tool. A low frequency gain of 63.9dB is obtained with a power dissipation of 1.38mW and a Unity Gain Frequency of 114 MHz.Item Improved Implementation of CRL and SCRL Gates for Ultra Low Power(IEEE, 2009) Gupta, AnuWorking with low frequency universal charge recovery logic (CRL) based NAND gate, the leakage current results in gradual charge up of the output node resulting in an incorrect output. A better implementation of the same circuit which increases the output resistance for the leakage current is used to mitigate this drawback in this paper. Also an analysis of the effect of rise time of clock edge on power dissipation of the split charge recovery logic (SCRL) based NAND gates has also been done.Item A novel sub-1 volt bandgap reference with all CMOS(ACM Digital Library, 2008-07) Gupta, AnuThis paper deals with the design of novel sub-1-V bandgap reference circuit using only MOS transistors in 0.18 µm CMOS technology, for a supply voltage of 1.8V. The circuit produces a voltage reference of 466.5 mV at 27°C with a temperature coefficient of 28.4 ppm/°C in the range of -20 to +120°C. The power supply rejection of circuit is -30 dB at 8 KHz and this rejection further increase to -50 dB at 10 KHz. Power dissipation is 3.98 µW. The circuit is also tested at four process corners. Circuit is simulated with Eldo SPICE.Item Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders(Emerald, 2005-12) Gupta, Anu; Shekhar, ChandraThe objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraintsItem Automation of clock distribution network design for digital integrated circuits using divide and conquer technique(Elsevier, 2006-07) Gupta, AnuOne of the most carefully engineered components of a digital integrated circuit is the clock distribution network. A clock is unarguably the most important signal and the network used for its distribution contributes to nearly half of the entire power dissipated by the IC. The design of a clock distribution network requires tremendous resources in terms of time and effort to achieve optimized results. This paper discusses the development of a new algorithm with smaller time complexity for automation of the design of clock distribution network that can greatly reduce the time and effort required, at the same time meeting the conditions set for delays and maximum allowable power dissipation.Item On-chip resistors can make a stable current reference(IEEE, 2008) Gupta, AnuA number of designs have been proposed for completely on-chip reference current generation but suffer varying degrees of drawbacks. The author presents a new design that provides a robust on-chip current reference circuit for submicron technologies without the usual disadvantagesItem Design of 10-bit Digital to Analog Converter Using Cascaded Operational Amplifier Topology(ACEEE, 2009) Gupta, AnuThis paper proposes an approach for designing a R-2R 10 bit Digital to Analog Converter (DAC) which could be made to operate at low voltage supply by efficiently exploiting the cascaded Operational Amplifier (Op-Amp) architecture. The DAC operates at a 3V power supply with a settling time of 50-100ns , dynamic range of around 50-60 dB for signals upto a frequency of 10Mhz. Graph & simulation results are provided to verify the stability of the Op-Amp used in DACItem Dual channel addition based FFT processor architecture for signal and image processing(ACM Digital Library, 2009-12) Gupta, Anu; Shekhar, Chandra; Asati, AbhijitThis paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fourier transform. Since multipliers are very power hungry elements in VLSI designs, they result in significant power consumption. So, the complex multiplication operations are realised using shift-and-add operations. The proposed algorithm performs all intermediate addition operation using a novel dual channel addition technique, which avoids carry propagation delay. Only in the last stage, carry look ahead adders are used to give final result. This dual channel addition algorithm reduces the critical delay path by 42% and 38.29% as compared to traditional and Maharatna approach respectively.