Department of Electrical and Electronics Engineering
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Item Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs(IEEE, 1997-12) Rao, V. RamgopalIn this paper we present experimental and simulation results on planar-doped-barrier MOSFETs (PDBFETs) and show the advantages that arise from the channel delta doping. Early and higher magnitude of velocity overshoot, suppression of avalanche multiplication, reduced hot-carrier problems are some of the advantages offered by PDBFETs over the conventional homogeneously doped MOSFETs in the sub 100 nm regime. Our low-temperature characterizations show clear ballistic transport in the fabricated 85 nm channel MOSFETs.Item Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics(IEEE, 2001) Rao, V. RamgopalIn this paper we look at the quantitative picture of fringing field effects by use of high-k dielectrics on the 70 nm node CMOS technologies. By using Monte-Carlo based techniques, we extract the degradation in gate-to-channel capacitance and the internal and external fringing capacitance components for varying values of K. The results clearly show the decrease in external fringing capacitance, increase in internal fringing capacitance and a slight decrease in overall capacitance, when the conventional SiO/sub 2/ is replaced by high-K dielectric. From the circuit point of view the lower total capacitance will increase the speed of the device, while the internal fringing capacitance will degrade the short-channel performance contributing to higher DIBL and drain leakage.Item Suppression of boron penetration by hot wire CVD polysilicon(IEEE, 2002) Rao, V. RamgopalIn the current and future deep sub-micron technologies, boron penetration through the gate dielectric is a severe reliability concern for the dual gate CMOS technology. In this paper we report results of our attempts to exploit the potential of Hot Wire CVD (HWCVD) for depositing poly-Si gate for CMOS technology. The effect of grain size of poly-Si gate on boron penetration is studied by varying the poly-Si grain size through variation in the HWCVD parameters.Item Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies(IEEE, 2006) Rao, V. RamgopalMOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage.Item Filament study of STI type drain extended NMOS device using transient interferometric mapping(IEEE, 2009-12) Rao, V. RamgopalWe present filament behavior of STI type DeNMOS devices using detailed Transient Interferometric Mapping experiments and 3D TCAD simulations. Device behavior at different TLP currents is discussed. The impact of localized base-push-out, power dissipation because of space charge build-up, regenerative NPN action and various events during the current filamentation are explored. By uniform turn-on of the device during base push-out the failure current could be improved by more than 2X.Item Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework(IEEE, 2010) Rao, V. RamgopalIn this paper, we present Auto-BET-AMS, an automated device, circuit and system-level simulation platform suitable for benchmarking emerging technologies at the end of the CMOS roadmap. This platform is suitable for technologists and circuit designers alike. One of the features of Auto-BET-AMS is that no advanced knowledge of device and circuit design is needed to perform a fair evaluation of emerging technologies. To enable this, the platform comes with a versatile multi-variable optimizer that can be used to quickly optimize devices and circuits for a set of specifications. Using Auto-BET-AMS it is possible to accurately design digital and analog circuits and assess them in conventional and emerging technologies. The platform can handle definitions of charge-based devices in either the compact model form or a look-up table form. The latter is needed for devices which do not have mature compact models developed for them. Several representative digital and analog circuits like buffer chain, SRAM cell, two-stage Miller Op-Amp, three-stage low-voltage Op-Amp, temperature compensated current reference and Miller OTA are optimized by considering PVT variations using Auto-BET-AMS. Additionally, the impact of parametric variations on these circuits is studied.Item Energy Efficient Lif Neuron Circuit Using Hybrid Cmos-Nems in 65 Nm Cmos Technology(IEEE, 2022-01) Rao, V. RamgopalIn this paper, we show that NEMS plays a key role to reduce the leakage current for designing the sub-threshold neuromorphic circuits in 65 nm CMOS technology. For the first time, we propose a novel energy efficient hybrid CMOS-NEMS leaky integrate and fire (LIF) neuron circuit and investigate the impact of fabricated sub-50 mV NEMS on the leakage power and overall energy consumption. As per the measurement results, the sub-50-mV NEMS having a small air gap of only 100 nm exhibits very low hysteresis (<20 mV), low turn ON delay (15 ns), and low sub-threshold swing of 2 mV/decade, a maximum ON-state conductance value of 0.1 A/(V·µm) with zero leakage current. We analyze the performance of a biologically-inspired energy efficient neuron circuit in terms of leakage power consumption with biologically plausible firing rates. Our results show that the proposed CMOS-NEMS neuron circuit gives around 8% reduction in energy per spike and 65% reduction in leakage power consumption than its equivalent CMOS design with the same complexity in standard 65 nm CMOS technology.Item Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique(IEEE, 2001-07) Rao, V. RamgopalIn this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current technique. The parasitic bipolar current gain /spl beta/ has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2D device simulations.Item Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations(IEEE, 2004-06) Rao, V. RamgopalThe performance of partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) devices is degraded by the body capacitance and body resistance, which depend strongly on the silicon film thickness. We show that the body RC time constant reduces up to a certain value of silicon film thickness, and then saturates. However, delay of a DTMOS circuit is affected not only by the RC delay of the body but also by the additional load capacitance, which appears due to the gate to body contact. In this paper, we propose a model for PDSOI-DTMOS circuit delay, taking the effect of body parasitics into account, and use it to study the circuit delay as a function of silicon film thickness. Using this model, we show that the optimum value of silicon film thickness is approximately equal to the depletion width in the silicon film in a typical sub-100-nm PDSOI-DTMOS technology.Item A new physical insight and 3D device modeling of STI type denmos device failure under ESD conditions(IEEE, 2009) Rao, V. RamgopalWe present experimental and simulation studies of STI type DeNMOS devices under ESD conditions. The impact of base-push-out, power dissipation because of space charge build-up and, regenerative NPN action, on the various phases of filamentation and the final thermal runaway is discussed. A modification of the device layout is proposed to achieve an improvement (~2X) in failure threshold (I T2 ).