Department of Electrical and Electronics Engineering

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Author: search.filters.author.Shekhar, ChandraSubject: search.filters.subject.CMOS technology

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    Design and Analysis of Modified Strong Arm Latch Comparator with Reduced Kickback Noise
    (Springer, 2024-10) Gupta, Anu; Shekhar, Chandra; Chaturvedi, Nitin
    This research paper introduces three techniques to reduce kickback noise in the Strong Arm Latch Comparator (SAL). The first technique focuses on utilizing high clock power and generating two clocks with different duty cycles. While initially addressing the issue by applying a single clock to the kickback-reducing circuit, the reduction of kickback noise did not meet the desired level. To overcome this limitation, a new design is proposed, incorporating a delay in the programmability of the kickback-reducing circuit, which effectively eliminates the need for kickback and clock requirements. A comparative study is conducted, evaluating all the designs, including the proposed design, based on power, delay, and analysis of various types of noise. Results show that the proposed technique outperforms other kickback-reducing designs in terms of propagation latency, power consumption, and kickback currents. Additionally, the impact of a comparator’s common-mode voltage (Vcm) on its performance in TSMC 180 nm CMOS technology is demonstrated using the Cadence Schematic Editor tool.
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    Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load
    (IEEE, 2009) Asati, Abhijit; Shekhar, Chandra
    The PMOS/NMOS width ratio (ß) and W/L ratio of NMOS device is an important ratio in the design of digital logic cells using conventional CMOS logic design style. In this paper we propose a simulation-based method applied to CMOS inverter to accurately estimate an optimum W/L ratio of NMOS device and PMOS/NMOS width ratio when fanout loading of 1, 4 and 8 cells of similar type are present. The appropriate selection of W/L ratio of NMOS device and PMOS/NMOS width ratio makes the digital design faster and reduces the power consumption.