Department of Electrical and Electronics Engineering
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Item Low temperature Hot-Wire CVD nitrides for deep sub-micron CMOS technologies(The International Society for Optical Engineering, 2000) Rao, V. RamgopalIn this work we report results on MNS capacitors with the silicon nitride films fabricated by using a novel Hot-Wire CVD technique. The dependence of deposition parameters on the film properties is looked into. Our electrical characterisation results on MNS capacitors show good oxide breakdown fields, and low leakage.Item Reliability studies on sub 100 nm SOI-MNSFETs(IEEE, 2000) Rao, V. RamgopalSOI MNSFETs with channel lengths down to 100 nm and having a Jet Vapor Deposited (JVD) silicon nitride (Si/sub 3/N/sub 4/) gate dielectric are fabricated and characterized. The JVD MNSFETs show comparable performance in comparison to conventional SiO/sub 2/ SOI-MOSFETs, in terms of low gate leakage, Si/sub 3/N/sub 4//Si interface quality and I/sub on//I/sub off/ ratio. In addition, the MNSFETs show better hot carrier reliability compared to conventional MOSFETs. Our results explore the worthiness of JVD Si/sub 3/N/sub 4/ as gate dielectric for future low power ULSI applications.Item Comparison of Sub-Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs(The Japan Society of Applied Physics, 2001) Rao, V. Ramgopal(Vp) well below the bandgap voltage of silicon has received widespread attention [1,2,3]. Substrate currents (Isue) for drain voltages down to 0.6V [1] and floating body effects in SOI devices down to 0.8V [2] were reported. This would imply that the impact ionization induced operational and reliability issues in nMOSFETs will continue to deca-nano meter device generations. Based on Monte Carlo simulations it was suggested that various modes of elecffon-electron interactions resulting in the high energy tail (HET) of the electron energy distribution are responsible for some elecfrons to have more energy than that gained from the lateral electric field (E61) [3,4]. An anomalous increase of the gate voltage at which the Isus peaks (Vcp"ud which can not be explained by HET is presented. We have also compared the sub-bandgap impact ionization in CONventional (CON) and Lateral Asymmetrical Channel (LAC) nMOSFETs of channel length l00nm. An enhancement of the increase in V60..1 is found in the LAC devices. Based on the results presented we propose quantization of inversion layer as an additional energy gain mechanism for the electrons.Item Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime(IEEE, 2000-09) Rao, V. RamgopalDrain bias dependence of gate oxide reliability is investigated on conventional (CON) and Lateral Asymmetric Channel (LAC) MOSFETs for low drain voltages that correspond to the real operating voltages for deep-sub-micron devices. For short channel devices, the oxide reliability improves drastically as drain bias increases. Device simulations showed that the vertical field distribution in the oxide is asymmetric for non-zero drain biases and this results in an asymmetric gate current distribution with the peak at the source end. By introducing an intentionally graded doping profile along the channel (LAC), the asymmetry in the vertical filed distribution can be enhanced with consequent improvement in gate oxide reliability.Item Multi-Frequency Transconductance Technique for Interface Characterization of Deep Sub-Micron SOI-MOSFETs(Elsevier, 2001-07) Rao, V. RamgopalA multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where conventional charge-pumping techniques cannot be applied. Using this multi-frequency technique, sub-micron SOI–MNSFETs with a SiN dielectric deposited by a novel jet-vapor-deposition (JVD) process are characterized. Results are compared with charge pumping results obtained on bulk MNSFETs with identically processed JVD nitrides.Item Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics(IEEE, 2001) Rao, V. RamgopalIn this paper we look at the quantitative picture of fringing field effects by use of high-k dielectrics on the 70 nm node CMOS technologies. By using Monte-Carlo based techniques, we extract the degradation in gate-to-channel capacitance and the internal and external fringing capacitance components for varying values of K. The results clearly show the decrease in external fringing capacitance, increase in internal fringing capacitance and a slight decrease in overall capacitance, when the conventional SiO/sub 2/ is replaced by high-K dielectric. From the circuit point of view the lower total capacitance will increase the speed of the device, while the internal fringing capacitance will degrade the short-channel performance contributing to higher DIBL and drain leakage.Item Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering(IEEE, 2001) Rao, V. RamgopalA comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D/sup 2/FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime.Item Reliability issues of ultra thin silicon nitride (a-SiN:H) by hot wire CVD for deep sub-micron CMOS technologies(SPIE, 2001) Rao, V. RamgopalThe reliability of gate dielectric is of high importance, especially as its thickness is reaching atomic dimensions. The gate leakage currents and the operating fields can be very high in devices with these ultra thin gate dielectrics. Several anomalous degradation mechanisms and breakdown characteristics are observed in these devices. New phenomena such as quasi breakdown and SILC are now considered important for accurate reliability assessment In this work we investigate a systematic reliability evaluation of high quality MNS devices made with ultra thin HWCVD nitride as the gate dielectric by taking into account these newer effects.Item Study of Degradation in Channel Initiated Secondary Electron Injection Regime(IEEE, 2001-09) Rao, V. RamgopalThis paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (IG) and substrate current (IB) has been studied for different values of substrate bias. Stress and charge pumping measurements have been carried out to study the degradation under identical substrate bias and gate current conditions. Results show that under identical gate current (programming time for flash memory cells), the degradation is less for higher negative substrate bias.Item The Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance(IEEE, 2001-09) Rao, V. RamgopalThe potential impact of high permittivity gate dielectrics on the circuit performance is studied over a wide range of gate dielectrics using 2-Dimensional device and monte-carlo simulations. It is found that there is a decrease in parasitic outer fringe capacitance, gate to channel capacitance and an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by high-K gate dielectrics. The lower parasitic outer fringe capacitance is beneficial in reducing the circuit delay, while an increase in internal fringe capacitance and decrease in gate to channel capacitance will degrade the gain, power dissipation and noise margin of the circuit. Also, from the circuit point of view, at the 70nm technology generation, the presence of an optimum Kgate for different subthreshold leakage currents has been identified