Department of Electrical and Electronics Engineering
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Item Analysis of temperature sensitive electrical performance of sputter grown Ni and Ni–Cr Schottky contacts on 4 H-SiC(Springer, 2024-11) Singh, Dheerendra; Mourya, Satyendra Kumar; Bhatt, Upendra MohanThis paper studies the temperature-dependent electrical transport properties of nickel (Ni) and nickel–chromium (Ni–Cr) sputtered on n-type 4 H-SiC substrate. Barrier inhomogeneities have been found to affect the electrical parameter of the Schottky barrier diode (SBD) from 323 to 423 K temperature range, We have done current–voltage characterization of Ni and Ni–Cr Schottky junctions. The barrier height , reverse saturation current , ideality factor and series resistance were obtained from I–V characteristics of Ni and Ni–Cr and these parameters are observed to be highly dependent on temperature. It has been observed that Ni–Cr contact has exhibited better electrical characteristics as well as thermal sensitivity as compared to Ni. This may be attributed to the smaller number of barrier inhomogeneities at the Ni–Cr/4 H-SiC interface. In the temperature range from 323 to 423 K, Ni and Ni–Cr-based Schottky contacts, Following observation has been noticed (a). Schottky barrier height (SBH) increased from 1.24 to 1.37 eV and 1.15 to 1.45 eV, (b). Ideality factors reduced from 3.76 to 2.61 and 3.20 to 2.53, (c). Series resistance decreased from 10.22 to 3.37 and 2.45 to 1.16 , and (d). Reverse leakage current to A and to A respectively. The V–T curves for both SBDs are investigated (for the same temperature range) to calculate their thermal sensitivity at and A, respectively. The V–T curves with linear behavior are used to calculate the thermal sensitivity coefficient , which was found to be 7.11 to 7.93 mV/K for the Ni–Cr SBD, and 7.1 to 20.01 mV/K for the Ni/4 H-SiC contacts. The sensitivity-current characteristics for the Ni/4 H-SiC SBD were found to be a non-linear comparison with Ni–Cr/4 H-SiC SBD, which may be attributed to the presence of a highly resistive and non-uniform coating of Ni at the interface.Item Reliability studies on sub 100 nm SOI-MNSFETs(IEEE, 2000) Rao, V. RamgopalSOI MNSFETs with channel lengths down to 100 nm and having a Jet Vapor Deposited (JVD) silicon nitride (Si/sub 3/N/sub 4/) gate dielectric are fabricated and characterized. The JVD MNSFETs show comparable performance in comparison to conventional SiO/sub 2/ SOI-MOSFETs, in terms of low gate leakage, Si/sub 3/N/sub 4//Si interface quality and I/sub on//I/sub off/ ratio. In addition, the MNSFETs show better hot carrier reliability compared to conventional MOSFETs. Our results explore the worthiness of JVD Si/sub 3/N/sub 4/ as gate dielectric for future low power ULSI applications.Item Comparison of Sub-Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs(The Japan Society of Applied Physics, 2001) Rao, V. Ramgopal(Vp) well below the bandgap voltage of silicon has received widespread attention [1,2,3]. Substrate currents (Isue) for drain voltages down to 0.6V [1] and floating body effects in SOI devices down to 0.8V [2] were reported. This would imply that the impact ionization induced operational and reliability issues in nMOSFETs will continue to deca-nano meter device generations. Based on Monte Carlo simulations it was suggested that various modes of elecffon-electron interactions resulting in the high energy tail (HET) of the electron energy distribution are responsible for some elecfrons to have more energy than that gained from the lateral electric field (E61) [3,4]. An anomalous increase of the gate voltage at which the Isus peaks (Vcp"ud which can not be explained by HET is presented. We have also compared the sub-bandgap impact ionization in CONventional (CON) and Lateral Asymmetrical Channel (LAC) nMOSFETs of channel length l00nm. An enhancement of the increase in V60..1 is found in the LAC devices. Based on the results presented we propose quantization of inversion layer as an additional energy gain mechanism for the electrons.Item Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime(IEEE, 2000-09) Rao, V. RamgopalDrain bias dependence of gate oxide reliability is investigated on conventional (CON) and Lateral Asymmetric Channel (LAC) MOSFETs for low drain voltages that correspond to the real operating voltages for deep-sub-micron devices. For short channel devices, the oxide reliability improves drastically as drain bias increases. Device simulations showed that the vertical field distribution in the oxide is asymmetric for non-zero drain biases and this results in an asymmetric gate current distribution with the peak at the source end. By introducing an intentionally graded doping profile along the channel (LAC), the asymmetry in the vertical filed distribution can be enhanced with consequent improvement in gate oxide reliability.Item Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering(IEEE, 2001) Rao, V. RamgopalA comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D/sup 2/FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime.Item Study of Degradation in Channel Initiated Secondary Electron Injection Regime(IEEE, 2001-09) Rao, V. RamgopalThis paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (IG) and substrate current (IB) has been studied for different values of substrate bias. Stress and charge pumping measurements have been carried out to study the degradation under identical substrate bias and gate current conditions. Results show that under identical gate current (programming time for flash memory cells), the degradation is less for higher negative substrate bias.Item Simulation Study of Non-Quasi Static Behaviour of MOS Transistors(TechConnect, 2002-04) Rao, V. RamgopalIn this paper, we study the “non-quasi static” (NQS) behaviour of MOS transistors using an exact quasi static Look-up Table (LUT) [1] MOSFET model implemented in a general-purpose circuit simulator SEQUEL [2], device simulator ISE-TCAD [3] and SPICE BSIM3v3 [4] QS and NQS models. An NMOS transistor of channel length 2 um is simulated using LUT, ISE and SPICE3 and terminal currents are qualitatively studied. The method for extraction of terminal charges, which are required for circuit simulation using the LUT approach also presented.Item Physical mechanisms for pulsed AC stress degradation in thin gate oxide MOSFETs(IEEE, 2002-07) Rao, V. RamgopalAn experimental study of the dielectric degradation under different AC stress conditions has been carried out using MOSFETs with 3.9 nm thick gate oxides. Bipolar and unipolar voltage pulses were used to stress the dielectric and interface state generation monitored. Pulse parameters (pulse levels, duty cycle, stress time, rise/fall times, and frequency) were systematically varied to understand the processes responsible for degradation. The experimental results give a good insight into the physical mechanisms responsible for interface degradation in ultra-thin gate oxides. The observations can be explained invoking carrier injection into the oxide followed by trapped-hole recombination.Item Effective dielectric thickness Scaling for High-K Gate Dielectric MOSFETs(Springer, 2011) Rao, V. RamgopalIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.Item Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-Micron SOI MOSFETs(Springer, 2001) Rao, V. RamgopalA study of parasitic bipolar junction transistor effects in single pocket thin film siliconon-insulators (SOI) nMOSFETs has been carried out. Characterization and simulation results show that parasitic bipolar junction transistor action is reduced in single pocket SOI MOSFETs in comparison to homogeneously doped conventional SOI MOSFETs. A novel Gate-Induced-Drain-Leakage (GIDL) current technique was used to characterize the SOI MOSFETs. 2 - D simulations were carried out to analyze the reduced parasitic bipolar junction effect in single pocket thin film SOI MOSFETs.