Department of Electrical and Electronics Engineering
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Item A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM(Elsevier, 2021-05) Vidhyadharan, SanjayThis paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an undesirable direct path between VDD and ground during certain ternary input signals, resulting in higher power consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which prevents a direct path between the power supply VDD and ground in all the possible ternary logic states. While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall decrease in Power Delay Product (PDP) is 86–97% in the proposed ultra-low-power ternary 32 nm CNTFET SRAM circuit and 87–99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional ternary SRAM circuits.Item Performance Evaluation of CNTFET based Dynamic Dual Edge Triggered Register(IEEE, 2013) Gupta, AnuCarbon Nanotube Field-Effect Transistor (CNTFET) with 1-D band structure providing better electrostatic control and high mobility due to ballistic transport operation has proved to be a promising alternative to the conventional CMOS technology. This paper presents a design, performance evaluation and comparative analysis for CNTFET based Dynamic Dual Edge Triggered D-Flip flop (DFF). Hspice simulation results shows that the presented DFF consumes significantly lower power and delay than its CMOS counterpart at 32 nm technology. The performance analysis of Serial in serial out register (SISO) based on these DFFs shows 88% reductions in the power delay product.Item Performance Evalution Of CNTFET-Based Sram Cell Design(Inter Science, 2012) Gupta, AnuCarbon Nanotube Field-Effect Transistor (CNTFET) technology with their excellent current capabilities, ballistic transport operation and superior thermal conductivities has proved to be a very promising and superior alternative to the conventional CMOS technology. A detailed analysis and simulation based assessment of circuit performance of this technology is presented here. As figures of merit speed, power consumption and stability are considered to evaluate the performance parameters of CNTFET-Based SRAM Cells with different chiral vectors for the optimum performance. A novel performance metric, presented as “SPR,” is used to assess these figures of merit. This comprehensive metric includes a metric of low power delay product (PDP) for write operation and high stability in the operation of a memory cell. It is shown that an 8T SRAM cell provides 73% higher SPR than Dual-Chiral based 6T SRAM cell for CNT technology and 124% higher SPR than its CMOS counterpart, thus attaining superior performance. The CNTFET-based 8T SRAM cell demonstrates that it provides high stability, low delay and low power, which is better than CNTFET-based 6T SRAM cell as well as CMOS SRAM cell.Item Design of CNTFET-based 2-bit ternary ALU for nanoelectronics(Taylor & Francis, 2013-08) Gupta, AnuThis article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.Item A Novel Design of Ternary Full Adder Using CNTFETs(Springer, 2014) Gupta, AnuThis paper proposes a novel design of pass transistor-based ternary full adder (TFA) cell using inherent binary nature (0, 1) of input carry in carbon nanotube field effect transistor (CNTFET) technology. A buffer circuit is added to get high performance without sacrificing the overall energy efficiency of the design. The use of pass transistor logic style leads to low power consumption. The proposed TFA is examined exhaustively, using Synopsys HSPICE simulator with 32 nm Stanford CNTFET model in various test conditions and at different supply voltages. The proposed design has high driving capability and is robust. At 0.9 V power supply, the proposed design shows 69 % reduction in power–delay product in comparison with its counterpart, recently published in the literature.Item Simulations of the CNFETs using different high-k gate dielectrics(IAES, 2020) Gupta, NavneetIn this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO2. It was also observed that as thickness of gate dielectric material reduces, drain current of CNFET increases. The outcomes of this study matches with the analytical results and hence confirm the results