BITS Faculty Publications

Permanent URI for this communityhttp://localhost:4000/handle/123456789/1867

Browse

Filters

1992 - 199925

Settings

Author: search.filters.author.Rao, V. RamgopalEnd date: 1999

Search Results

Now showing 1 - 10 of 25
  • No Thumbnail Available
    Item
    Radiation Induced Interface State Generation in Nitrided and Reoxidized Nitrided Gate Oxides
    (AIP, 1992-01) Rao, V. Ramgopal
    Reoxidized nitrided oxide is compared with nitrided oxides and dry SiO2 for radiation‐induced interface‐state generation (ΔDitm) and midgap voltage shifts (ΔVmg). The suppression of ΔDitm observed with heavy nitridation or reoxidation is explained in terms of the trapped‐hole recombination model together with the shifting of the location of the trapped positive charge away from the Si interface. This model can also explain the effect of nitrogen annealing on nitrided oxides.  
  • No Thumbnail Available
    Item
    Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs
    (IEEE, 1997-12) Rao, V. Ramgopal
    In this paper we present experimental and simulation results on planar-doped-barrier MOSFETs (PDBFETs) and show the advantages that arise from the channel delta doping. Early and higher magnitude of velocity overshoot, suppression of avalanche multiplication, reduced hot-carrier problems are some of the advantages offered by PDBFETs over the conventional homogeneously doped MOSFETs in the sub 100 nm regime. Our low-temperature characterizations show clear ballistic transport in the fabricated 85 nm channel MOSFETs.
  • No Thumbnail Available
    Item
    The Planar-Doped-Barrier FET:MOSFET Overcomes Conventional Limitations
    (IEEE, 1997-10) Rao, V. Ramgopal
    Introducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel lengths Planar-Doped-BarrierFETs were fabricated. Investigations on electrical characteristics and carrier transport show the predicted improvements compared to classical MOSFETs.
  • No Thumbnail Available
    Item
    Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology
    (IEEE, 1998-10) Rao, V. Ramgopal
    SOI devices are of great interest, especially for low power and low voltage applications. To achieve this goal, the device threshold voltage must be lowered while maintaining low sub-threshold leakage. However, when devices are downscaled, short channel effects (SCE) and hot carrier effects (HCE) also become severe issues in SOI MOSFETs. Symmetric halo implantations are widely used in bulk MOSFETs to improve SCE. Recently, asymmetric channel implantation or "pocket implantation" on the source end was introduced in bulk MOSFETs to adjust the threshold voltage and improve the device SCE and HCE. In this work, for the first time, we introduce large tilt angle implantation in the SOI MOSFET to form a lateral asymmetric channel (LAC) doping profile after gate formation. High concentration channel doping near the source end reduces DIBL and threshold voltage roll-off while low doping concentration near the drain side ensures high mobility. Furthermore, the peak electric field near the drain is reduced and impact ionization is less serious compared to conventional devices.
  • No Thumbnail Available
    Item
  • No Thumbnail Available
    Item
    Plasma process induced abnormal 1/f noise behavior in deep sub-micron MOSFETs
    (IEEE, 1998) Rao, V. Ramgopal
    The effect of plasma damage on the MOSFET's flicker noise properties is examined in this work. We observe an abnormal noise peak in the 1/f noise spectrum at around 2 kHz which is a characteristic of the plasma damage. The dependence of the noise peak on the plasma induced degradation was studied in virgin n- and p-channel MOSFETs and this peak is shown to correlate well with the amount of damage in the p-MOSFETs.
  • No Thumbnail Available
    Item
    Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics
    (IEEE, 1999-09) Rao, V. Ramgopal
    High-K gate dielectrics have been under extensive investigation for use in sub-lOOnm MOSFETs to suppress gate leakage. However, thicker gate dielectrics can result in degradation of the electrical performance due to increased fringing fields from the gate to source/drain. In this paper, the capacitance degradation resulting from this effect is analyzed and a simple technique to model this effect is presented.
  • No Thumbnail Available
    Item
    Hot-Carrier Induced Interface Degradation in Jet Vapor Deposited SiN MNSFETs as Studied by a Novel Charge Pumping Technique
    (IEEE, 1999) Rao, V. Ramgopal
    Metal-Nitride-Semiconductor f"'En:" with channel lengths down to 100 nm and a novel .leI Vapor f)eposited (JVD) SiN gate dielectric are fabricated and characterized for their hot-carrier reliability. A novel charge pumping technique is employed to characterize the stress induced interface degradation (?f such MN5WETs' in comparison to MOSJ-1n:\, having thermal Si(h gale oxide. Under identical substrate current during stress, MNSFE1's show less inte1jcu:e-state generation and resulting drain current degradation jbr various channel lengths, stress time and supply voltage. The time and vollage dependence of hot-carrier degradation has been found (0 he distinctly d􀁮tferent for MN.)'F'ETs compared (0 conventional Si02 MOSFET'i.
  • No Thumbnail Available
    Item
    Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS
    (IEEE, 1999) Rao, V. Ramgopal
    The effects of channel engineering on device performance have been extensively investigated. The lateral asymmetric channel (LAC) MOSFETs show significantly higher I/sub dsat/ and g/sub msat/, lower I/sub off/, and superior short-channel performance compared with double-halo (DH) and conventional MOSFETs by effectively utilizing the velocity overshoot effects. It is demonstrated that the device switching speed of the LAC device at V/sub DD/=0.6 V is equivalent to that of a conventional device operated at V/sub DD/=1.5 V.
  • No Thumbnail Available
    Item
    100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric
    (IEEE, 1999) Rao, V. Ramgopal
    Metal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.