BITS Faculty Publications
Permanent URI for this communityhttp://localhost:4000/handle/123456789/1867
Browse
54 results
Search Results
Item Analysis of temperature sensitive electrical performance of sputter grown Ni and Ni–Cr Schottky contacts on 4 H-SiC(Springer, 2024-11) Singh, Dheerendra; Mourya, Satyendra Kumar; Bhatt, Upendra MohanThis paper studies the temperature-dependent electrical transport properties of nickel (Ni) and nickel–chromium (Ni–Cr) sputtered on n-type 4 H-SiC substrate. Barrier inhomogeneities have been found to affect the electrical parameter of the Schottky barrier diode (SBD) from 323 to 423 K temperature range, We have done current–voltage characterization of Ni and Ni–Cr Schottky junctions. The barrier height , reverse saturation current , ideality factor and series resistance were obtained from I–V characteristics of Ni and Ni–Cr and these parameters are observed to be highly dependent on temperature. It has been observed that Ni–Cr contact has exhibited better electrical characteristics as well as thermal sensitivity as compared to Ni. This may be attributed to the smaller number of barrier inhomogeneities at the Ni–Cr/4 H-SiC interface. In the temperature range from 323 to 423 K, Ni and Ni–Cr-based Schottky contacts, Following observation has been noticed (a). Schottky barrier height (SBH) increased from 1.24 to 1.37 eV and 1.15 to 1.45 eV, (b). Ideality factors reduced from 3.76 to 2.61 and 3.20 to 2.53, (c). Series resistance decreased from 10.22 to 3.37 and 2.45 to 1.16 , and (d). Reverse leakage current to A and to A respectively. The V–T curves for both SBDs are investigated (for the same temperature range) to calculate their thermal sensitivity at and A, respectively. The V–T curves with linear behavior are used to calculate the thermal sensitivity coefficient , which was found to be 7.11 to 7.93 mV/K for the Ni–Cr SBD, and 7.1 to 20.01 mV/K for the Ni/4 H-SiC contacts. The sensitivity-current characteristics for the Ni/4 H-SiC SBD were found to be a non-linear comparison with Ni–Cr/4 H-SiC SBD, which may be attributed to the presence of a highly resistive and non-uniform coating of Ni at the interface.Item Size quantization effect in the channel of a 2D nano scale dual gate MOSFET(AIP, 2020-05) Sarkar, NiladriIn this work, we studied the size quantization effects in the channel of a low dimensional MOSFET using a Self-Consistent Quantum Method where Schrodinger-Poisson equations are solved for determining the electron density for 3nm × 3nm and 12nm×12nm 2D channels. The 3nm×3nm channel MOSFET show the peak of the electron density at the middle whereas the 12nmξ12nm channel MOSFET shows the accumulation of the electrons at the oxide/semiconductor interface. The electron density in the channel is obtained using density matrix formalism from the density matrix . A block diagonal Hamiltonian Matrix [H] is constructed for the oxide/channel/oxide 2D structure for the dual gate MOSFET. This structure is discretized and Finite-Difference method is used for constructing the matrix equation. We also show the effect of effective mass on the overall channel electron density distribution. This analysis is very important and gives an understanding of the Physics of the channel electron density for Nano-Scale DevicesItem Effect of size quantization and quantum capacitance on the threshold voltage of a 2D nanoscale dual gate MOSFET(IOP, 2020-09) Sarkar, NiladriThe size quantization effect in the channel of a 2D nanoscale MOSFET is studied using a self-consistent quantum method. Under this, Schrodinger-Poisson equations are solved for determining the electron density for 2D device channels from 3 nm × 3 nm to 100 nm × 100 nm. The lower dimension channels show a peak of the electron density at the middle whereas higher dimension channels show the accumulation of the electrons at the oxide/semiconductor interface. Also, the role of quantum capacitance on the threshold voltages of these nanoscale devices is investigated as a function of channel dimensions and electron effective masses. It is observed that not only the size but the electron effective masses dominate the conductivity of the channel for such nanoscale devices. Here, the channel electron densities are obtained using density matrix formalism. A block diagonal Hamiltonian Matrix [H] is constructed for this oxide/channel/oxide 2D structure and the channel is discretized by using the finite-difference method. This analysis is important for understanding the physics of the size quantization and its effect on the threshold voltage.Item Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs(IEEE, 1997-12) Rao, V. RamgopalIn this paper we present experimental and simulation results on planar-doped-barrier MOSFETs (PDBFETs) and show the advantages that arise from the channel delta doping. Early and higher magnitude of velocity overshoot, suppression of avalanche multiplication, reduced hot-carrier problems are some of the advantages offered by PDBFETs over the conventional homogeneously doped MOSFETs in the sub 100 nm regime. Our low-temperature characterizations show clear ballistic transport in the fabricated 85 nm channel MOSFETs.Item The Planar-Doped-Barrier FET:MOSFET Overcomes Conventional Limitations(IEEE, 1997-10) Rao, V. RamgopalIntroducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel lengths Planar-Doped-BarrierFETs were fabricated. Investigations on electrical characteristics and carrier transport show the predicted improvements compared to classical MOSFETs.Item Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology(IEEE, 1998-10) Rao, V. RamgopalSOI devices are of great interest, especially for low power and low voltage applications. To achieve this goal, the device threshold voltage must be lowered while maintaining low sub-threshold leakage. However, when devices are downscaled, short channel effects (SCE) and hot carrier effects (HCE) also become severe issues in SOI MOSFETs. Symmetric halo implantations are widely used in bulk MOSFETs to improve SCE. Recently, asymmetric channel implantation or "pocket implantation" on the source end was introduced in bulk MOSFETs to adjust the threshold voltage and improve the device SCE and HCE. In this work, for the first time, we introduce large tilt angle implantation in the SOI MOSFET to form a lateral asymmetric channel (LAC) doping profile after gate formation. High concentration channel doping near the source end reduces DIBL and threshold voltage roll-off while low doping concentration near the drain side ensures high mobility. Furthermore, the peak electric field near the drain is reduced and impact ionization is less serious compared to conventional devices.Item Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics(IEEE, 1999-09) Rao, V. RamgopalHigh-K gate dielectrics have been under extensive investigation for use in sub-lOOnm MOSFETs to suppress gate leakage. However, thicker gate dielectrics can result in degradation of the electrical performance due to increased fringing fields from the gate to source/drain. In this paper, the capacitance degradation resulting from this effect is analyzed and a simple technique to model this effect is presented.Item Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS(IEEE, 1999) Rao, V. RamgopalThe effects of channel engineering on device performance have been extensively investigated. The lateral asymmetric channel (LAC) MOSFETs show significantly higher I/sub dsat/ and g/sub msat/, lower I/sub off/, and superior short-channel performance compared with double-halo (DH) and conventional MOSFETs by effectively utilizing the velocity overshoot effects. It is demonstrated that the device switching speed of the LAC device at V/sub DD/=0.6 V is equivalent to that of a conventional device operated at V/sub DD/=1.5 V.Item 100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric(IEEE, 1999) Rao, V. RamgopalMetal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.Item Reliability studies on sub 100 nm SOI-MNSFETs(IEEE, 2000) Rao, V. RamgopalSOI MNSFETs with channel lengths down to 100 nm and having a Jet Vapor Deposited (JVD) silicon nitride (Si/sub 3/N/sub 4/) gate dielectric are fabricated and characterized. The JVD MNSFETs show comparable performance in comparison to conventional SiO/sub 2/ SOI-MOSFETs, in terms of low gate leakage, Si/sub 3/N/sub 4//Si interface quality and I/sub on//I/sub off/ ratio. In addition, the MNSFETs show better hot carrier reliability compared to conventional MOSFETs. Our results explore the worthiness of JVD Si/sub 3/N/sub 4/ as gate dielectric for future low power ULSI applications.