Department of Electrical and Electronics Engineering

Permanent URI for this collectionhttp://localhost:4000/handle/123456789/1925

Browse

End date: 2009Subject: search.filters.subject.CMOS technology

Search Results

Now showing 1 - 10 of 10
  • No Thumbnail Available
    Item
    Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs
    (IEEE, 1997-12) Rao, V. Ramgopal
    In this paper we present experimental and simulation results on planar-doped-barrier MOSFETs (PDBFETs) and show the advantages that arise from the channel delta doping. Early and higher magnitude of velocity overshoot, suppression of avalanche multiplication, reduced hot-carrier problems are some of the advantages offered by PDBFETs over the conventional homogeneously doped MOSFETs in the sub 100 nm regime. Our low-temperature characterizations show clear ballistic transport in the fabricated 85 nm channel MOSFETs.
  • No Thumbnail Available
    Item
    Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics
    (IEEE, 2001) Rao, V. Ramgopal
    In this paper we look at the quantitative picture of fringing field effects by use of high-k dielectrics on the 70 nm node CMOS technologies. By using Monte-Carlo based techniques, we extract the degradation in gate-to-channel capacitance and the internal and external fringing capacitance components for varying values of K. The results clearly show the decrease in external fringing capacitance, increase in internal fringing capacitance and a slight decrease in overall capacitance, when the conventional SiO/sub 2/ is replaced by high-K dielectric. From the circuit point of view the lower total capacitance will increase the speed of the device, while the internal fringing capacitance will degrade the short-channel performance contributing to higher DIBL and drain leakage.
  • No Thumbnail Available
    Item
    Suppression of boron penetration by hot wire CVD polysilicon
    (IEEE, 2002) Rao, V. Ramgopal
    In the current and future deep sub-micron technologies, boron penetration through the gate dielectric is a severe reliability concern for the dual gate CMOS technology. In this paper we report results of our attempts to exploit the potential of Hot Wire CVD (HWCVD) for depositing poly-Si gate for CMOS technology. The effect of grain size of poly-Si gate on boron penetration is studied by varying the poly-Si grain size through variation in the HWCVD parameters.
  • No Thumbnail Available
    Item
    Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies
    (IEEE, 2006) Rao, V. Ramgopal
    MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage.
  • No Thumbnail Available
    Item
    Filament study of STI type drain extended NMOS device using transient interferometric mapping
    (IEEE, 2009-12) Rao, V. Ramgopal
    We present filament behavior of STI type DeNMOS devices using detailed Transient Interferometric Mapping experiments and 3D TCAD simulations. Device behavior at different TLP currents is discussed. The impact of localized base-push-out, power dissipation because of space charge build-up, regenerative NPN action and various events during the current filamentation are explored. By uniform turn-on of the device during base push-out the failure current could be improved by more than 2X.
  • No Thumbnail Available
    Item
    Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique
    (IEEE, 2001-07) Rao, V. Ramgopal
    In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current technique. The parasitic bipolar current gain /spl beta/ has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2D device simulations.
  • No Thumbnail Available
    Item
    Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations
    (IEEE, 2004-06) Rao, V. Ramgopal
    The performance of partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) devices is degraded by the body capacitance and body resistance, which depend strongly on the silicon film thickness. We show that the body RC time constant reduces up to a certain value of silicon film thickness, and then saturates. However, delay of a DTMOS circuit is affected not only by the RC delay of the body but also by the additional load capacitance, which appears due to the gate to body contact. In this paper, we propose a model for PDSOI-DTMOS circuit delay, taking the effect of body parasitics into account, and use it to study the circuit delay as a function of silicon film thickness. Using this model, we show that the optimum value of silicon film thickness is approximately equal to the depletion width in the silicon film in a typical sub-100-nm PDSOI-DTMOS technology.
  • No Thumbnail Available
    Item
    A new physical insight and 3D device modeling of STI type denmos device failure under ESD conditions
    (IEEE, 2009) Rao, V. Ramgopal
    We present experimental and simulation studies of STI type DeNMOS devices under ESD conditions. The impact of base-push-out, power dissipation because of space charge build-up and, regenerative NPN action, on the various phases of filamentation and the final thermal runaway is discussed. A modification of the device layout is proposed to achieve an improvement (~2X) in failure threshold (I T2 ).
  • No Thumbnail Available
    Item
    Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load
    (IEEE, 2009) Asati, Abhijit; Shekhar, Chandra
    The PMOS/NMOS width ratio (ß) and W/L ratio of NMOS device is an important ratio in the design of digital logic cells using conventional CMOS logic design style. In this paper we propose a simulation-based method applied to CMOS inverter to accurately estimate an optimum W/L ratio of NMOS device and PMOS/NMOS width ratio when fanout loading of 1, 4 and 8 cells of similar type are present. The appropriate selection of W/L ratio of NMOS device and PMOS/NMOS width ratio makes the digital design faster and reduces the power consumption.
  • No Thumbnail Available
    Item
    A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers
    (IEEE, 2009) Gupta, Anu
    A very simple technique to achieve low settling time is presented. It is based on the combination of class AB differential input stages, local common-mode feedback (LCMFB), and clamping circuit which provides additional current boosting, keeping the gain-bandwidth product (GBW) nearly constant. The slew enhancement is provided by an auxiliary circuit which is activated only during transients. The design is based on the ldquoTSMC 180 nm CMOS technologyrdquo