Department of Electrical and Electronics Engineering
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Item Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs(IEEE, 1997-12) Rao, V. RamgopalIn this paper we present experimental and simulation results on planar-doped-barrier MOSFETs (PDBFETs) and show the advantages that arise from the channel delta doping. Early and higher magnitude of velocity overshoot, suppression of avalanche multiplication, reduced hot-carrier problems are some of the advantages offered by PDBFETs over the conventional homogeneously doped MOSFETs in the sub 100 nm regime. Our low-temperature characterizations show clear ballistic transport in the fabricated 85 nm channel MOSFETs.Item The Planar-Doped-Barrier FET:MOSFET Overcomes Conventional Limitations(IEEE, 1997-10) Rao, V. RamgopalIntroducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel lengths Planar-Doped-BarrierFETs were fabricated. Investigations on electrical characteristics and carrier transport show the predicted improvements compared to classical MOSFETs.Item Sub-0.18 /spl mu/m SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology(IEEE, 1998-10) Rao, V. RamgopalSOI devices are of great interest, especially for low power and low voltage applications. To achieve this goal, the device threshold voltage must be lowered while maintaining low sub-threshold leakage. However, when devices are downscaled, short channel effects (SCE) and hot carrier effects (HCE) also become severe issues in SOI MOSFETs. Symmetric halo implantations are widely used in bulk MOSFETs to improve SCE. Recently, asymmetric channel implantation or "pocket implantation" on the source end was introduced in bulk MOSFETs to adjust the threshold voltage and improve the device SCE and HCE. In this work, for the first time, we introduce large tilt angle implantation in the SOI MOSFET to form a lateral asymmetric channel (LAC) doping profile after gate formation. High concentration channel doping near the source end reduces DIBL and threshold voltage roll-off while low doping concentration near the drain side ensures high mobility. Furthermore, the peak electric field near the drain is reduced and impact ionization is less serious compared to conventional devices.Item Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics(IEEE, 1999-09) Rao, V. RamgopalHigh-K gate dielectrics have been under extensive investigation for use in sub-lOOnm MOSFETs to suppress gate leakage. However, thicker gate dielectrics can result in degradation of the electrical performance due to increased fringing fields from the gate to source/drain. In this paper, the capacitance degradation resulting from this effect is analyzed and a simple technique to model this effect is presented.Item Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS(IEEE, 1999) Rao, V. RamgopalThe effects of channel engineering on device performance have been extensively investigated. The lateral asymmetric channel (LAC) MOSFETs show significantly higher I/sub dsat/ and g/sub msat/, lower I/sub off/, and superior short-channel performance compared with double-halo (DH) and conventional MOSFETs by effectively utilizing the velocity overshoot effects. It is demonstrated that the device switching speed of the LAC device at V/sub DD/=0.6 V is equivalent to that of a conventional device operated at V/sub DD/=1.5 V.Item 100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric(IEEE, 1999) Rao, V. RamgopalMetal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.Item Application of charge pumping technique for sub-micron MOSFET characterization(Elsevier, 1998-11) Rao, V. RamgopalIn this paper, charge pumping technique for MOSFET interface characterization will be reviewed. The basic principles of charge pumping technique will be elaborated and its evolution as an excellent tool for a thorough characterization of MOSFET interface properties will be illustrated. Published results regarding the applicability of charge pumping technique for a study of sub-micron MOSFET interface and its degradation under various electrical stress conditions and radiation will be analyzed. The effect of geometric components on charge pumping current as well as the recent reports of single interface trap characterization in sub-micron MOSFETs will be described. The application of charge pumping technique at cryogenic temperatures and in other MOS based devices will also be included.Item Electric field tailoring in MBE-grown vertical sub-100 nm MOSFETs(Elsevier, 1998-05) Rao, V. RamgopalWe introduce the concept of electric-field-tailoring in MBE-grown vertical metal-oxide semiconductor field-effect transistors (MOSFETs) and show that significant improvements in terms of supply voltage, current and speed are achievable in such MOSFETs by employing a planar-doped-barrier MOSFET (PDBFET) concept. Investigation of electrical characteristics and carrier transport in sub-100 nm channel PDBFETs shows the predicted improvements compared with classical MOSFETs.Item A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping(Elsevier, 1999-09) Rao, V. RamgopalLateral Asymmetric Channel (LAC) MOSFETs with channel lengths down to 0.1 μm have been fabricated and characterized for their electrical performance. Using charge pumping, we show, for the first time, channel VT profiles obtained experimentally, demonstrating realization of asymmetric channel MOSFETs down to 0.1 μm channel lengths. Our detailed experimental characterizations show improved performance for LAC MOSFETs over conventional MOSFETs, in addition to excellent hot-carrier reliability. Based on 2-D device simulation results, we attribute the improved hot-carrier reliability in LAC MOSFETs to the reduced peak lateral electric field in the channel.Item A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs(Elsevier, 1999-05) Rao, V. RamgopalA new charge pumping (CP) technique is proposed to obtain the spatial profile of interface-state density (Nit) and oxide charges (Not) near the drain junction of hot-carrier stressed MOSFETs. Complete separation of Nit from Not is achieved by using a direct noniterative method. The pre-stress CP edge is corrected for the charges associated with both the generated Nit and Not. A closed form model is developed to predict the stress-induced incremental CP current. The damage distributions are obtained after fitting the model with experimental data.