Department of Electrical and Electronics Engineering
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Item Plasma process induced abnormal 1/f noise behavior in deep sub-micron MOSFETs(IEEE, 1998) Rao, V. RamgopalThe effect of plasma damage on the MOSFET's flicker noise properties is examined in this work. We observe an abnormal noise peak in the 1/f noise spectrum at around 2 kHz which is a characteristic of the plasma damage. The dependence of the noise peak on the plasma induced degradation was studied in virgin n- and p-channel MOSFETs and this peak is shown to correlate well with the amount of damage in the p-MOSFETs.Item Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics(IEEE, 1999-09) Rao, V. RamgopalHigh-K gate dielectrics have been under extensive investigation for use in sub-lOOnm MOSFETs to suppress gate leakage. However, thicker gate dielectrics can result in degradation of the electrical performance due to increased fringing fields from the gate to source/drain. In this paper, the capacitance degradation resulting from this effect is analyzed and a simple technique to model this effect is presented.Item 100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric(IEEE, 1999) Rao, V. RamgopalMetal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.Item Study of Degradation in Channel Initiated Secondary Electron Injection Regime(IEEE, 2001-09) Rao, V. RamgopalThis paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (IG) and substrate current (IB) has been studied for different values of substrate bias. Stress and charge pumping measurements have been carried out to study the degradation under identical substrate bias and gate current conditions. Results show that under identical gate current (programming time for flash memory cells), the degradation is less for higher negative substrate bias.Item The Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance(IEEE, 2001-09) Rao, V. RamgopalThe potential impact of high permittivity gate dielectrics on the circuit performance is studied over a wide range of gate dielectrics using 2-Dimensional device and monte-carlo simulations. It is found that there is a decrease in parasitic outer fringe capacitance, gate to channel capacitance and an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by high-K gate dielectrics. The lower parasitic outer fringe capacitance is beneficial in reducing the circuit delay, while an increase in internal fringe capacitance and decrease in gate to channel capacitance will degrade the gain, power dissipation and noise margin of the circuit. Also, from the circuit point of view, at the 70nm technology generation, the presence of an optimum Kgate for different subthreshold leakage currents has been identifiedItem Optimization of Single Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliability(IEEE, 2002-09) Rao, V. RamgopalSingle halo (SH) MOSFETs are recently proposed for mixed signal applications in view of their superior analog performance such as gain, transconductance, output resistance etc [1]. In this work, we investigate the hot carrier degradation behaviour of SH and conventional p-MOSFETs using specific stress conditions appropriate for analog applications. The degradation of analog device parameters due to Cannel Hot carrier (CHC) stress and its implications on circuit operation are discussed.Item Physical mechanisms for pulsed AC stress degradation in thin gate oxide MOSFETs(IEEE, 2002-07) Rao, V. RamgopalAn experimental study of the dielectric degradation under different AC stress conditions has been carried out using MOSFETs with 3.9 nm thick gate oxides. Bipolar and unipolar voltage pulses were used to stress the dielectric and interface state generation monitored. Pulse parameters (pulse levels, duty cycle, stress time, rise/fall times, and frequency) were systematically varied to understand the processes responsible for degradation. The experimental results give a good insight into the physical mechanisms responsible for interface degradation in ultra-thin gate oxides. The observations can be explained invoking carrier injection into the oxide followed by trapped-hole recombination.Item Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs(IEEE, 2003) Rao, V. RamgopalThe effect of programming biases on the cycling endurance of NOR flash EEPROMs is studied under CHE and CHISEL operation. CHE degradation increases at higher control gate bias (V/sub CG/) and is insensitive to changes in drain bias (V/sub D/) CHISEL degradation is insensitive to changes in both V/sub CG/, and V/sub D/. Furthermore, CHISEL always shows lower degradation when compared to CHE under identical bias and similar programming time. The possible physical mechanisms responsible for the above behavior are clarified by using full band Monte-Carlo simulations.Item Understanding the NBTI Degradation in Halo- Doped Channel p-MOSFETs(IEEE, 2004-07) Rao, V. RamgopalThe role of initial interface damage for negative bias temperature instability (NBTI) degradation has been examined for short channel MOSFET devices. In this paper we present a detailed study of the role of initial silicon-oxide interface quality on the NBTI degradation. Hole density and oxide fields are important parameters responsible for NBTI degradation. Our results show that NBTI degradation is independent of initial interface quality.Item Sub-threshold Swing Degradation due to Localized Charge Storage in SONOS Memories(IEEE, 2004-07) Rao, V. RamgopalThis paper discusses the effect of localized charge storage on sub-threshold swing and threshold voltage in silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cells. By analyzing the change in potential contours, it has been shown that the change in sub-threshold swing is correlated to fringing of electric field lines, and hence to the gate-to-substrate capacitance.